![]() ![]() With the revenue from the Z80, the company built its own chip factories and grew to over a thousand employees over the following two years. The first working samples were delivered in March 1976, and it was officially introduced on the market in July 1976. The Z80 was conceived by Federico Faggin in late 1974 and developed by him and his 11 employees starting in early 1975. The Z80 is an 8-bit microprocessor introduced by Zilog as the startup company's first product. So my answer for the question "Is there any harm in doing this?", is NO, even you will have more flexibility and achieve higher baud rates.The Z80's original DIP40 chip package pinout ![]() Therefore, sampling each time of RX signal gives you the ability to communicate higher baud rates with little extra resources, which you have huge amount of inside FPGAs nowadays.Ä«y the way, believe it or not but x8 or x16 tick generation circuit also spent resources of FPGAs! It is not a free tick signal. However, today with thousands of gates in an FPGA, most of the times adaptation to newer requirements quickly and modularity gains importance, especially for small low-end protocols such as UART, SPI, I2C etc. IMHO, because UART is an old protocol, at that time using less resources for circuit was crucial. Then I will ask what if you have 50 MHz instead of 100 MHz? This time the error rate is 67.817/70 = 3%. So I need to generate 1/(BAUDx8) second tick, which is 67.81 ns. Okay you can say well for this case I can use x8 oversampling. So you will generate a baud tick of 30 ns instead of 33.908 ns, where the error rate is 33.908/30 = 13% !!! But with 100 MHz clock freq your resolution is 10 ns, so with counting up to 3, you get 30 ns. I want to ask a question for x8 or x16 supporters, can you communicate with a device using UART with 1_843_200 bps baud rate with even a high clock frequency such as 100 MHz? Well with x16 sampling, you need 1/(BAUDx16) second tick, which is 33.908 ns. So you need some wierd clock frequencies to implement such UART logic with your FPGA. Well first of all the code will throw assertion with these constants! Because 25_000_000 can not be divided by 115200 with no residue. Parameter ClkFrequency = 25000000 // 25MHz If(ClkFrequency ![]()
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